1. Field of the Invention
The present invention relates to a reconfigurable logic block. More specifically, it relates to a control circuit for reading and writing circuitry data for a logic circuit in a memory element.
2. Description of the Related Art
A reconfigurable logic block rewrites a configuration of a logic circuit using software, and is effective as a means of providing an adaptable system large-scale integration (LSI). However, the reconfigurable logic block is large-scale since a memory array, which stores reconfiguration data for a to-be-rewritten logic circuit, is required. Furthermore, when rewriting a logic circuit, it is necessary to serially transmit a large quantity of circuitry data from a memory to a circuit via a bus line. Thus, a great deal of time is required for logic circuit reconfiguration.
In order to solve these problems, it is effective to embed the memory array, which serves to switch over interconnects in the reconfigurable logic block, on the interconnection layer of the reconfigurable logic block.
In other words, since the typical memory array is large-scale, the area of the reconfigurable logic block may be reduced by being fabricated in a multi-level structure. Furthermore, since the interconnect distance between the memory array and the logic circuit may decrease and signals may be transmitted in parallel, the transmission speed of signals for rewriting the interconnects of the logic circuit may increase (Refer to IEICE Tech. Report. ICD2002-10, 2002, p. 13).
In a current method, since writing and reading for the memory array is implemented, for example, in series in units of 16 bits, a great deal of time is required with a large-scale logic circuit. Furthermore, even with rewriting logic circuit interconnects, reconfiguration is implemented in series, requiring a great deal of time.
In the case of transmitting data in parallel between the memory array and the logic circuit, a circuit for writing to and reading from memory elements needs to be miniaturized in order to miniaturize the reconfigurable logic block. Heretofore, a sense amplifier is used for reading circuitry data for the logic circuit. However, the sense amplifier is larger than a memory element. Since each memory element must be provided with a write circuit and a sense amplifier, it is difficult to miniaturize the entire reconfigurable logic block.
The present invention was devised in response to the forgoing requirements, and aims to provide a reconfigurable logic block and a control circuit, so as to miniaturize a write or readout circuit for a memory array, miniaturize the entire circuit by providing a multi-level memory, and decrease logic circuit reconfiguration time.